2014 IEDM International Electron Devices Meeting


2014 IEEE International
Electron Devices Meeting

Hilton San Francisco Union Square
333 O'Farrell Street
San Francisco, CA USA
December 15-17, 2014


Chris Burke
co-Media Relations Director
+1 919 872 8172

Gary Dagastine
co-Media Relations Director
+1 518 785 2724

The IEEE International Electron Devices Meeting (IEDM) is the world's premier forum for the presentation of advances in microelectronic, nanoelectronic and bioelectronic devices. The IEDM spotlights technical breakthroughs in a wide range of applications such as logic, memory, MEMs, sensors, displays, flexible electronics, biomedical imaging, power electronics and energy harvesting. The 60th annual IEDM conference program includes an overall emphasis on circuit and process technology interactions, bio-sensors and bioMEMS, energy harvesting, power devices, sensors, magnetics, spintronics, two-dimensional electronics, devices for non-Boolean computing, and multiferroics.

Welcome to the Editor Press Center. Check back periodically for photo and caption updates. The following press materials may be downloaded from this site for pre-conference publicity for the IEDM:

2014 IEDM Press Kit

IEDM Press Releases
- Lead Release
- Tip Sheet (“highlights” of IEDM Technical Program)
- Late-News Release

2014 IEDM Photos

Selected images from the abstracts are presented in two formats:
- Word file with images associated with a highlighted
paper and the caption
- JPEG file with individual high-resolution Images.

4.2 "Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers"
M. Goto et al, NHK
Image With Caption
4.2, 3D "Pixel-Parallel" Image Processing, NHK
High Resolution Images
4.2 Figure 1
4.2 Figure 2
4.2 Figure 9
4.2 Figure 10

6.2 "Process Integration of a 27nm, 16Gb Cu ReRAM"
J. Zahurak et al, Micron Technology
Image With Caption
6.2, Fully Integrated 27nm 16Gb ReRAM, Micron
High Resolution Images
6.2 Figure 1
6.2 Figure 2
6.2 Figure 3

8.1, "Two-Dimensional Nanoelectromechanical Systems (2D NEMS) via Atomically-Thin Semiconducting Crystals Vibrating at Radio Frequencies"
Philip X.-L. Feng et al, Case Western Reserve University
Image With Caption
8.1 Figure 2 (a) & (b) - Scanning electron microscopy image (top) and atomic force microscopy image (bottom)
8.1 Additional Image - 2D NEMS
High Resolution Images

8.1 Figure 2
8.1 Additional Image: 2D NEMS

8.2 "Integrated On-Chip Energy Storage Using Porous-Silicon Electrochemical Capacitors"
D.S. Gardner et al, Intel
Image With Caption
8.2, Porous Silicon for Integrated On-Chip Energy Storage, Intel
High Resolution Images

8.2 Figure 1c
8.2 Figure 3c
8.2 Figure 4
8.2 Figure 5

9.1 "FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node"
Q. Liu et al, ST Microelectronics/IBM Technology Development Alliance
Image With Caption
9.1, Strained FDSOI Devices for the 10nm Node, STMicro & IBM Tech Dev Alliance
High Resolution Images

9.1 Figure 3a
9.1 Figure 3b

10.5 "A CMOS-Compatible, Integrated Approach to Hyper- and Multispectral Imaging"
A. Lambrechts et al, Imec
Image With Caption
10.5 Eliminating Bulky Optics in Hyperspectral Cameras, Imec.docx
High Resolution Images

10.5 Figure 1
10.5 Figure 4a
10.5 Figure 4b
10.5 Figure 5a
10.5 Figure 5b
10.5 Figure 6

16.2 "Dual-Channel CMOS Co-Integration with Si NFET and Strained-SiGe PFET in Nanowire Device Architecture Featuring Sub-15nm Gate Length"
P. Nguyen et al, CEA-LETI
Image With Caption
16.2, Dual-Channel Nanowire Transistors, CEA-LETI
High Resolution Images

16.2 Figure 4-1
16.2 Figure 4-2
16.2 Figure 4-3
16.2 Figure 4-5
16.2 Figure 4 combined

25.1 "Novel Intrinsic and Extrinsic Engineering for High-Performance High-Density Self-Aligned InGaAs MOSFETs: Precise Channel Thickness Control and Sub-40-nm Metal Contacts"
J. Lin et al, Massachusetts Institute of Technology
Image With Caption
25.1, Real-World Performance of Scaled InGaAs Devices, MIT
High Resolution Images

25.1 Figure 1a
25.1 Figure 1b
25.1 Figure 2a
25.1 Figure 2b
25.1 Figure 2c
25.1 Figure 15a
25.1 Figure 15b
25.1 Figure 15c

26.5 "Solution-Processed Poly-Si TFTs Fabricated at a Maximum Temperature of 150°C"
M. Trifunovic et al, Delft University of Technology
Image With Caption
26.5, Polysilicon Transistors on Arbitrary Substrates Such As Paper, Delft University
High Resolution Images

26.5 Figure 3-1
26.5 Figure 3-2

27.6 "Flexible High-Performance Nonvolatile Memory by Transferring GAA Silicon Nanowire SONOS onto a Plastic Substrate"
J.-M. Choi et al, KAIST
Image With Caption
27.6, Flexible High-Performance Nonvolatile Memory, KAIST
High Resolution Images

27.6 Figure 1
27.6 Figure 3

28.2 "Challenge of MOS/MTJ-Hybrid Nonvolatile Logic-in-Memory Architecture in Dark-Silicon Era,"
T. Hanyu et al, Tohoku University
Image With Caption
28.2 Nonvolatile Logic-in-Memory Technology, Tohoku University
High Resolution Image

28.2 Figure 1

28.6 "Highly Dependable 3-D Stacked Multicore Processor System Module Fabricated Using Reconfigured Multichip-on-Wafer 3-D Integration Technology"
K.-W. Lee et al, Tohoku University
Image With Caption
28.6, 3D Integration of Diverse Technologies for Self-Driving Vehicles, Tohoku University
High Resolution Image

28.6 Figure 17

29.2 "55-μA GexTe1-x/Sb2Te3 Superlattice Topological-Switching Random-Access Memory (TRAM) and Study of Atomic Arrangement in Ge-Te and Sb-Te Structures"
N. Takaura et al, Low-Power Electronics Association and Project (LEAP)
Image With Caption
29.2, TRAM-A New Memory Type, LEAP project
High Resolution Images

29.2 Figure 1
29.2 Figure 13

31.1 "Bio-MEMS Towards Single-Molecule Characterization"
H. Fujita, University of Tokyo
Image With Caption
31.1, Combating Alzheimer's Disease with MEMS Technology, University of Tokyo
High Resolution Images

31.1 Figure 1
31.1 Figure 2

32.1 "Electrical Characterization of FinFET with Fins Formed by Directed Self Assembly at 29 nm Fin Pitch Using a Self-Aligned Fin Customization Scheme"
H. Tsai et al, IBM
Image With Caption
32.1, FinFETs Formed by Directed Self-Assembly
High Resolution Images

32.1 Figure 3
32.1 Figure 6
32.1 Figure 6 large
32.1 Figure 8

Attendance at IEDM is complimentary for the press. If you plan to attend, please let us know. Also, the conference organizers are planning to have a press luncheon at the beginning of the IEDM to discuss the most interesting papers and the major technology trends evident in this year's program. We encourage journalists to attend it, and details will be provided in November.

Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact one of us for the additional information or interviews you may need.

Your registration/attendance questions also can be answered by the Conference Manager Phyllis Mahoney, at phyllism@widerkehr.com or by telephone at +1 301 527 0900.