June 1-4, 2008
Hyatt Regency
San Francisco Airport Hotel Burlingame, California

PRESS CONTACTS

Gary Dagastine
co-Media Relations Director for IITC '08
518-785-2724 office
email:gdagastine@nycap.rr.com

Christopher Burke
BtB Marketing Communications
co-Media Relations Director for IITC '08
919-872-8172 office
919-637-3510 cell
email:cburke@btbmarketing.com

Wendy Walker
IITC Administrator
301-527-0900 Ext. 104,
Fax: 301-527-0994
email:iitc@his.com

Garth Miller
Media Relations Executive
for IITC
919-872-8172 office
919-923-3505 cell
email:gmiller@btbmarketing.com

WELCOME TO THE EDITOR PRESS CENTER.
The IITC is the premier conference for semiconductor interconnect technology. Interconnect is the wiring system that connects transistors within a computer chip. It also refers to chip-to-package connections and chip-to-chip connections. The need for such a specialized conference arises from the fact that for today’s most-advanced chips, interconnect gets in the way of performance. Yet without the ever-higher performance we have come to expect from computer chips, progress in the electronics field may stall.

At the IITC, some 600 scientists and engineers from the industry and from academia will come together to present and discuss relevant issues and technologies. The IITC will be preceded by a short course on Sunday June 1, and also will feature a product exhibition and supplier seminars.

DOWNLOADS:
The following press materials may be downloaded from this site for
pre-conference publicity for the IITC:

IITC Lead Release

IITC Tipsheet

IITC Advance Program

2008 IITC Photos
San Fransisco, CA image with caption
San Fransisco, CA high-resolution image (jpeg)
IITC logo (jpeg)

Selected images from the abstracts are presented in two formats:
Word file with all images associated with a highlighted paper and the caption.
JPEG file with individual, high-resolution images.

Paper 2.3, "A 3D-IC Technology with Integrated Microchannel Cooling,"
D. Sekar et al, Georgia Institute of Technology, IBM and Nanonexus

Image with Caption
2.3 Microfluidic Heat Sinks for 3D Chips:

High Resolution Images
2.3 Figure 5

Paper 4.6, "Hybrid e-CMP/CMP Process with Non-Contact Electrode Pad," 
S. Kondo et al, Selete and Japan Roki Techno Co., Ltd

Image with Caption
4.6 No Contact, No Damage:

High Resolution Images
4.6 Figure 1
4.6 Figure 2

Paper 10.2, “Hybrid e-CMP/CMP Process with Non-Contact Electrode Pad,”
N. Nakamura et al, Toshiba

Image with Caption
10.2 One of Two New Ways To Make Multi-Level Air Gaps:

High Resolution Images
10.2 Figure 1
10.2 Figure 2

Paper 10.3, “300 mm Multi Level Air Gap Integration for Edge Interconnect Technologies and Specific High Performance Applications,”
R. Gras et al, STMicroeelctronics, CEA-Leti-MINATEC, and CNRS-LTM

Image with Caption
10.3 Another New Way To Make Multi-Level Air Gaps:

High Resolution Images
10.3 Figure 2
10.3 Figure 6a
10.3 Figure 6b
10.3 Figure 7

Paper 11.5, "Low-Temperature Plasma-Oxidation Process for Reliable Tantalum-Oxide (TaO) Decoupling Capacitors," I.Kume et al, NEC

Image with Caption
11.5 Reliable Integrated MIM Decoupling Capacitors: 

High Resolution Images
11.5 Figure 1

Paper 12.3, "Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit," G. Close et al, Toshiba and Stanford University

Image with Caption
12.3 1st Test Of Carbon Nanotubes As Interconnects In A Real Circuit:

High Resolution Images
12.3 Figure 1
12.3 Figure 5

Paper 12.4, "Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current," A. Kawabat et al, MIRAI-Selete and Waseda University

Image with Caption
12.4 Robust, Low-Temperature Nanotube Vias

High Resolution Images
12.4 Figure 2
12.4 Figure 3